The invention is directed to a method and to an arrangement for monitoring the consistence of successive binary code signal groups in data processing equipment, where a predictive calculation of parity bit is made in response to a preceding code signal group.
U.S. Pat. No. 4,074,229 discloses such a method, particularly with reference to the code signal groups employed for addressing an instruction word memory. From the established address, the predictive parity bit belonging to the successor address is identified for selecting the memory for the write-in of an instruction, and is deposited in a bit position provided in addition to the instruction. The parity bit belonging to the successor address is therefore always available with the readout of an instruction. This parity bit is then intermediately stored and, when the instruction memory is selected by the successor address, it is compared to the parity bit directly derived from this successor address. An error signal is generated when there is inequality of comparison.
Even when storing only the predictive parity bit instead of the entire instruction word, this method requires a memory comprising a plurality of memory locations corresponding in number to the totality of memory addresses. The hardware outlay required for such a memory is very high and depends on the number of code signal groups.